Vertical cell-type semiconductor device having protective pattern

ABSTRACT

According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.14/151,288, filed on Jan. 9, 2014, which claims priority under 35 U.S.C.§119 to Korean Patent Application No. 10-2013-0029103, filed on Mar. 19,2013, the entire contents of each of the above-referenced applicationsare hereby incorporated by reference.

BACKGROUND

1. Field

The present disclosure relates to a vertical cell-type semiconductordevice having a protective pattern, and/or a method of fabricating thesame.

2. Description of Related Art

As integrated circuits are downscaled faster and faster, a verticalcell-type semiconductor device in which components formed in a verticaldirection, has been proposed.

In a process of fabricating the vertical cell-type semiconductor device,it may be desirable to limit (and/or prevent) the components of thesemiconductor device from being damaged by an etchant used to removesacrificial layers, and to reduce (and/or minimize) voids or seams frombeing present in gate electrodes when the gate electrodes are formed.

SUMMARY

Example embodiments of inventive concepts relate to a vertical cell-typesemiconductor device and/or a method of fabricating the same.

Example embodiments of inventive concepts also relate to a verticalcell-type semiconductor device having a protective pattern resistant toa wet etching process, and a method of fabricating the same.

Example embodiments of inventive concepts relate to a vertical cell-typesemiconductor device having protective patterns of a new type, which areconfigured to remove or reduce (and/or minimize) voids or seams in gateelectrodes when the gate electrodes are formed, and/or a method offabricating the same.

According to example embodiments of inventive concepts, a semiconductordevice includes: a substrate; a stacked structure including interlayerinsulating layers and gate electrodes alternately stacked on thesubstrate, the stacked structure defining a through-hole, each of thegate electrodes including a portion in which a vertical width thereof isreduced with the approach to one end thereof; and a vertical structurefilling the through-hole. The vertical structure includes a gap-fillpattern in a middle of the through-hole, a channel pattern surroundingan outer surface of the gap-fill pattern, and a gate dielectric layersurrounding an outer surface of the channel pattern. The gate dielectriclayer includes a tunneling layer in contact with the channel pattern, acharge trap layer in contact with the tunneling layer, a barrier layerin contact with the charge trap layer, and protective patterns. Each oneof the protective patterns is between the barrier layer and one of thegate electrodes, and each one of the protective patterns extends betweentwo of the interlayer insulating layers and the protective patternssurround the portions the gate electrodes in which the vertical widththereof is reduced.

In example embodiments, the protective patterns may include an oxide ofsilicon, such as oxidized silicon.

In example embodiments, each one of the gate electrodes may include anupper surface opposite a lower surface, a first lateral surface oppositea second lateral surface, and an upper inclined surface opposite a lowerinclined surface. The first lateral surface may connect one end of theupper surface to one end of the lower surface. The upper inclinedsurface connected to one end of the second lateral surface and an otherend of the upper surface, and the lower inclined surface may connect another end of the second lateral surface and an other end of the lowersurface. A length of the second lateral surface may be shorter than alength of the first lateral surface.

In example embodiments, each one of the protective patterns may includean upper part between a lower surface of one of the interlayerinsulating layers above and the upper inclined surface of an adjacentone of the gate electrodes, a lower part between the lower surface ofone of the interlayer insulating layers below and the lower inclinedsurface of the adjacent one of the gate electrodes, and a body partconnecting the upper part and the lower part.

In example embodiments, the upper part of each one of the protectivepatterns may include an inclined inner surface in contact with the upperinclined surface of one of the gate electrodes, and the lower part ofeach one of the protective patterns may include an inclined innersurface in contact with the lower inclined surface of one of the gateelectrodes.

In example embodiments, the semiconductor device may further includeblocking layers. Each one of the blocking layers may have one surface incontact with the upper surface, lower surface, upper inclined surface,lower inclined surface, and second lateral surface of one of the gateelectrodes. Each one of the blocking layers may have an other surface incontact with parts of two interlayer insulating layers, the inclinedupper and lower inner surfaces and one surface of the body part of oneof the protective patterns.

In example embodiments, the body part of each one of the protectivepatterns may include a protrusion that protrudes into the through-hole.

In example embodiments, the barrier layer may contact exposed surfacesof the interlayer insulating layers and the protrusions of the bodyparts of the protective patterns.

In example embodiment, a contact electrode may be on the gap-fillpattern and contact the channel pattern.

In example embodiments, the semiconductor device may further include:capping layers on the stacked structure, wherein the capping layers maydefine a hole exposing an upper surface of the contact electrode.

In example embodiments, a conductive interconnection may be on thecapping layers. The conductive interconnection may be electricallyconnected to the exposed contact electrode.

According to example embodiments of inventive concepts, a semiconductordevice includes: a substrate, a stacked structure including interlayerinsulating layers and gate electrodes alternately stacked on thesubstrate, the stacked structure defining a through-hole, each of thegate electrodes including a portion in which a vertical width thereof isreduced with the approach to one end thereof; and a vertical structurein the through-hole. The vertical structure includes a gap-fill patternin a middle of the through-hole, a channel pattern surrounding an outersurface of the gap-fill pattern, and a gate dielectric layer surroundingan outer surface of the channel pattern. The gate dielectric layerincludes a tunneling layer in contact with the channel pattern, a chargetrap layer in contact with the tunneling layer, a protective layer incontact with the charge trap layer, and protective patterns that areintegral with the protective layer. The protective patterns extend tothe gate electrodes, and surround the portions of the gate electrodes inwhich the vertical width is reduced.

According to example embodiments of inventive concepts, a semiconductordevice includes: a substrate; a stacked structure including interlayerinsulating layers and gate electrodes alternately stacked on thesubstrate, the stacked structure defining a through-hole over thesubstrate, the gate electrodes each including a first portion betweenthe through-hole and a second portion of the gate electrodes; a channelpattern extending vertically in the through-hole over the substrate; atunneling layer surrounding the channel pattern; a charge trap layersurrounding the tunneling layer; and protective patterns surrounding thefirst portions of the gate electrodes. The protective patterns arebetween the first portions of the gate electrodes and the charge traplayer.

In example embodiments, the first portions of the gate electrodes mayeach have a thickness that gradually reduces from the second portions ofthe gate electrodes towards the through-hole, and the protectivepatterns may be arranged so they do not surround the second portions ofthe gate electrodes.

In example embodiments, a barrier layer may be between the protectivepatterns and the charge trap layer.

In example embodiments, a protective layer may extend vertically in thethrough-hole between the charge trap layer and the protective patterns.Each one of the protective patterns may extend from a side of theprotective layer to surround the first portion of one of the gateelectrodes.

In example embodiments, the protective patterns may include an oxide ofsilicon, the interlayer insulating layer may include an oxide, and theoxide of silicon in the protective patterns may be more compact than theoxide of the interlayer insulating layers.

Details of example embodiments of inventive concepts are included in thedetailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages of example embodimentsof inventive concepts will be apparent from the more particulardescription of non-limiting embodiments of inventive concepts, asillustrated in the accompanying drawings in which like referencecharacters refer to the same parts throughout the different views. Thedrawings are not necessarily to scale, emphasis instead being placedupon illustrating the principles of inventive concepts. In the drawings:

FIG. 1A is a cross-sectional view showing a vertical cell-typesemiconductor device according to example embodiments of inventiveconcepts;

FIG. 1B illustrates an enlarged view of part A of FIG. 1A;

FIG. 1C illustrates an enlarged view of part B of FIG. 1B;

FIG. 2A illustrates a cross-sectional view showing a vertical cell-typesemiconductor device according to example embodiments of inventiveconcepts;

FIG. 2B illustrates an enlarged view of part C of FIG. 2A;

FIG. 3A illustrates a cross-sectional view showing a vertical cell-typesemiconductor device according to example embodiments of inventiveconcepts;

FIG. 3B illustrates an enlarged view of part D of FIG. 3A;

FIGS. 4A to 4Q illustrate process cross-sectional views showing a methodof fabricating a vertical cell-type semiconductor device according toexample embodiments of inventive concepts in a process sequence;

FIGS. 5A to 5F illustrate process cross-sectional views showing a methodof fabricating a vertical cell-type semiconductor device according toexample embodiments of inventive concepts in a process sequence;

FIGS. 6A to 6D illustrate process cross-sectional views showing a methodof fabricating a vertical cell-type semiconductor device according toexample embodiments of inventive concepts in a process sequence;

FIG. 7 illustrates a conceptual view showing a semiconductor module,which includes one of the semiconductor devices according to exampleembodiments of inventive concepts;

FIG. 8 illustrates a conceptual block diagram showing an electromagneticsystem, which includes one of the semiconductor devices according toexample embodiments of inventive concepts;

FIG. 9 illustrates a schematic block diagram showing an electromagneticsystem, which includes a semiconductor device according to exampleembodiments of inventive concepts; and

FIG. 10 schematically illustrates a mobile electromagnetic appliance,which includes a semiconductor devices according to example embodimentsof inventive concepts.

DETAILED DESCRIPTION

Example embodiments of inventive concepts will now be described morefully with reference to the accompanying drawings in which someembodiments are shown. These example embodiments of inventive conceptsmay, however, be embodied in different forms and should not be construedas limited to the embodiments set forth herein. Rather, these exampleembodiments of inventive concepts are provided so that this disclosureis thorough and complete and fully convey the scope of inventiveconcepts to those skilled in the art. In the drawings, the sizes andrelative sizes of layers and regions may be exaggerated for clarity.Like reference numerals in the drawings denote like elements, and thustheir description may be omitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements. Other words used to describe relationships betweenelements should be interpreted in a like fashion (e.g., “between” versus“directly between,” “adjacent” versus “directly adjacent,” “on” versus“directly on”, etc.). As used herein the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, A, B, etc.may be used herein to describe various elements, components, regions,layers and/or sections. These elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the figures. It will be understood thatthe spatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

The terminology used herein to describe particular embodiment and is notintended to limit the scope of example embodiments of inventiveconcepts. The articles “a,” “an,” and “the” are singular in that theyhave a single referent, however the use of the singular form in thepresent document should not preclude the presence of more than onereferent. In other words, elements referred to in the singular maynumber one or more, unless the context clearly indicates otherwise. Itwill be further understood that the terms “comprises,” “comprising,”“includes,” and/or “including,” when used herein, specify the presenceof stated features, items, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, items, steps, operations, elements, components, and/orgroups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures). As such, variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,example embodiments of inventive concepts should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe present inventive concept.

Unless otherwise defined, all terms (including technical and scientificterms) used herein are to be interpreted as is customary in the art towhich example embodiments of inventive concepts belong. It will befurther understood that terms in common usage should also be interpretedas is customary in the relevant art and not in an idealized or overlyformal sense unless expressly so defined herein.

FIG. 1A illustrates a cross-sectional view showing a vertical cell-typesemiconductor device according to example embodiments of inventiveconcepts. FIG. 1B illustrates an enlarged view of part A of FIG. 1A.FIG. 1C illustrates an enlarged view of part B of FIG. 1B.

Referring to FIGS. 1A and 1B, a vertical cell-type semiconductor device100A according to example embodiments of inventive concepts may includea stacked structure 100S formed on a substrate 102, first to thirdcapping layers 110, 126, and 128 covering the stacked structure 100S, atrench T passing through the first to third capping layers 110, 126, and128 in vertical and horizontal directions, a through-hole H that isspaced apart from the trench T and passes through the stacked structure100S and the first capping layer 110, first and second verticalstructures VS1 a and VS2 filling the through-hole H and the trench Trespectively, a contact pad 124 disposed on a gap-fill pattern 122, acontact electrode 140 passing through the second and third cappinglayers 126 and 128 to be in contact with the contact pad 124, and aconductive interconnection 142 disposed on an upper surface of the thirdcapping layer 128 in contact with the contact electrodes 140.

The stacked structure 100S may include interlayer insulating layers 104and gate electrodes 134GS, 134C, and 134SS. The gate electrodes 134C maybe alternately stacked with interlayer insulating layers 104 between thegate electrodes 134GS and 134SS. The gate electrode 134GS may be on alowermost one of the interlayer insulating layers 104. An uppermost oneof the interlayer insulating layers 104 may be on the gate electrode134SS. The interlayer insulating layers 104 may include silicon oxide(SiO₂), and the gate electrodes 134GS, 134C, and 134SS may include aconductive material, such as tungsten (W), copper (Cu), aluminum (Al),titanium (Ti), titanium nitride (TiN), tantalum (Ta), or doped silicon(n- or p-type Si).

The first vertical structure VS1 a may include a gate dielectric layerGDa formed along an inner wall of the through-hole H, a cylindricalchannel pattern 120 formed along an inner wall of the gate dielectriclayer GDa, and a gap-fill pattern 122 formed in the center of thethrough-hole H so as to fill the interior of the channel pattern 120.The channel pattern 120 may enclose an outer surface of the gap-fillpattern 122, and the gate dielectric layer GDa may enclose an outersurface of the channel pattern 120. An upper surface of the gap-fillpattern 122 may be located lower than an upper end of the through-holeH. Since the through-hole H may be circular when viewed in a plan view,the first vertical structure VS1 a may look to be symmetrically formedon the inner wall of the through-hole H when viewed in a longitudinalsectional view.

A lower portion of the channel pattern 120 may be in contact with asurface of the substrate 102 and the surface of the substrate 102 may bea bottom surface of the through-hole H. An upper portion of the channelpattern 120 may be in contact with an entire outer surface of thecontact pad 124. The channel pattern 120 may include a semiconductormaterial, such as single crystalline silicon or poly-crystallinesilicon.

The substrate 102 may include a semiconductor substrate, such as asilicon (Si) substrate, a silicon germanium (SiGe) substrate, or asemiconductor-on-insulator (SOI) substrate. For example, thesemiconductor-on-insulator (SOI) substrate may be a silicon-on-insulatorsubstrate.

The contact pad 124 may include a conductive or semiconductor material,such as single crystalline silicon or poly-crystalline silicon. Thefirst to third capping layers 110, 126, and 128 may include aninsulating material, such as silicon oxide. The contact electrode 140and the conductive interconnection 142 may include a conductivematerial, such as copper (Cu), tungsten (W), or aluminum (Al).

Among the plurality of gate electrodes 134GS, 134C, and 134SS, thelowermost gate electrode 134GS may be used as a ground selection gateelectrode 134GS, and the uppermost gate electrode 134SS may be used as astring selection gate electrode 134SS. Gate electrodes 134C formedbetween the ground selection gate electrode 134GS and the stringselection gate electrode 134SS may be used as cell gate electrodes 134C.Thus, the ground selection gate electrode 134GS, the gate dielectriclayer GDa that is in contact with the ground selection gate electrode134GS, and the channel pattern 120 may constitute a ground selectiontransistor. The cell gate electrodes 134C, the gate dielectric layer GDathat is in contact with the cell gate electrodes 134C, and the channelpattern 120 may constitute cell transistors. The string selection gateelectrode 134SS, the gate dielectric layer GDa that is in contact withthe string selection gate electrode 134SS, and the channel pattern 120may constitute a string selection transistor. In this way, the groundselection transistor, the numerous cell transistors, and the stringselection transistor may form a unit vertical cell string. Theconductive interconnection 142 may be used as a bit line.

The second vertical structure VS2 may have the shape of a fence fillingthe trench T. The second vertical structure VS2 may include siliconoxide.

Further referring FIGS. 1B and 1C, the gate electrodes 134GS, 134C, and134SS of the vertical cell-type semiconductor device 100A according toexample embodiments of inventive concepts may each include an uppersurface GB1, a lower surface GB2, a first lateral surface GB3, a secondlateral surface GB4, an upper inclined surface GB5 between the uppersurface GB1 and the first lateral surface GB4, and a lower inclinedsurface GB6 between the lower surface GB2 and the second lateral surfaceGB4. A vertical length of the second lateral surface GB4 may be shorterthan that of the first lateral surface GB3. The gate electrodes 134GS,134C, and 134SS may have a shape in which a vertical width W1 is reducedwith the approach to the second lateral surface GB4.

The gate dielectric layer GDa may include protective patterns 112 a,each of which partly encloses each of the gate electrodes 134GS, 134C,and 134SS, a barrier layer 114 that is in contact with exposed lateralsurfaces of the protective patterns 112 a and the interlayer insulatinglayers 104, a charge trap layer 116 that is in contact with the barrierlayer 114, and a tunneling layer 118 that have one surface of which isin contact with the charge trap layer 116, and the other surface ofwhich is in contact with the channel pattern 120. Further, the gatedielectric layer GDa may further include blocking layers 132 disposedamong the gate electrodes 134GS, 134C, and 134SS, the protectivepatterns 112 a, and the interlayer insulating layers 104.

The blocking layers 132 may each enclose the upper surface GB1, thelower surface GB2, the first lateral surface GB3, the second lateralsurface GB4, the upper inclined surface GB5, and the lower inclinedsurface GB6 of each of the gate electrodes 134GS, 134C, and 134SS. Thus,the blocking layers 132 may each include an upper inclined part BK1 anda lower inclined part BK2 enclosing the upper inclined surface GB5 andthe lower inclined surface GB6 of each of the gate electrodes 134GS,134C, and 134SS.

The protective patterns 112 a may include upper parts BB1 partlyenclosing the upper inclined surfaces GB5 of the gate electrodes 134GS,134C, and 134SS and/or the upper inclined parts BK1 of the blockinglayers 132, lower parts BB2 enclosing the lower inclined surface GB6 ofthe gate electrodes 134GS, 134C, and 134SS and/or the lower inclinedparts BK2 of the blocking layers 132, and body parts BB3 enclosing thesecond lateral surfaces GB4 of the gate electrodes 134GS, 134C, and134SS and/or the lateral surfaces of the blocking layers 132. The upperpart BB1 of each protective pattern 112 a may have an inclined innersurface BB1 a that is in contact with the upper inclined part BK1 ofeach blocking layer 132. The lower part BB2 of each protective pattern112 a may have an inclined inner surface BB2 a that is in contact withthe lower inclined part BK2 of each blocking layer 132.

Each protective pattern 112 a may include oxidized silicon more compact(e.g., higher density) than oxide included in the interlayer insulatinglayer 104 and barrier layer 114. A process of forming the protectivepatterns 112 a may include a radical oxidation process.

A lateral profile of the barrier layer 114 may protrude or be recessedalong profiles of the protective patterns 112 a. That is, the barrierlayer 114 may be in contact with portions P, each of which protrudesinto the through-hole H in the body part BB3 of each protective pattern112 a, and one lateral surface of each interlayer insulating layer 104.The barrier layer 114 may include (deposited) silicon oxide.

In some cases, the barrier layer 114 may be omitted.

The charge trap layer 116 may be in contact with the barrier layer 114.The charge trap layer 116 is an information storage layer that functionsto trap and hold electric charges implanted from the channel pattern 120through the tunneling layer 118, or to eliminate the electric chargestrapped in the tunneling layer 118. A material of which the charge traplayer 116 is formed may include silicon nitride (SiN_(x)), aluminumoxide (Al₂O₃), zirconium oxide (ZrO), hafnium oxide (HfO), or lanthanumoxide (LaO), (e.g., a material having a higher dielectric constantcompared to silicon oxide.

The tunneling layer 118 is a passage through which the electronsintroduced from the channel pattern 120 move to the charge trap layer116. The tunneling layer 118 may include silicon oxide or nitrogen-dopedsilicon oxide.

Each blocking layer 132 limits (and/or prevents) the electric chargesstored in the charge trap layer 116 from being tunneled to each cellgate electrode 134C, and thereby can improve information storagecapability. Each blocking layer 132 may be in contact with an upperand/or lower surface of each interlayer insulating layer 104. Eachblocking layer 132 may include an insulating material having a high workfunction (and/or dielectric constant), such as aluminum oxide (Al₂O₃) orhafnium oxide (HfO₂).

The vertical cell-type semiconductor device 100A according to exampleembodiments of inventive concepts includes the barrier layer 114 betweenthe gate electrodes 134GS, 134C, and 134SS and the charge trap layer116, and the protective patterns 112 a more compact than the barrierlayer 114, and thereby can limit (and/or prevent) the charge trap layer116 and the channel pattern 120 from being damaged by an etchant.

Further, since each of the gate electrodes 134GS, 134C, and 134SS has ashape in which the vertical width W1 thereof is reduced with theapproach to one end thereof at an arbitrary position by each protectivepattern 112 a, no or a (reduced and/or minimum amount of) voids or seamscan be present in the gate electrodes 134GS, 134C, and 134SS.

FIG. 2A illustrates a cross-sectional view showing a vertical cell-typesemiconductor device according to example embodiments of inventiveconcepts. FIG. 2B illustrates an enlarged view of part C of FIG. 2A.

Referring to FIGS. 2A, 2B, and 1C a vertical cell-type semiconductordevice 100 b according to example embodiments of inventive concepts mayinclude a stacked structure 100S in which interlayer insulating layers104 and gate electrodes 134GS, 134C, and 134SS are alternately andrepeatedly stacked on a substrate 102, first to third capping layers110, 126, and 128 covering the stacked structure 100S, a through-hole Hpassing through the stacked structure 100S and the first capping layer110, a trench T passing through the stacked structure 100S and the firstto third capping layers 110, 126, and 128, first and second verticalstructures VS1 b and VS2 filling the through-hole H and the trench Trespectively, a contact pad 124 being in contact with the first verticalstructure VS1 b, a contact electrode 140 passing through the second andthird capping layers 126 and 128 to be in contact with the contact pad124, and a conductive interconnection 142 formed on an upper surface ofthe third capping layer 128 in contact with the contact electrode 140.

The first vertical structure VS1 b may include a cylindrical gatedielectric layer GDb formed along an inner wall of the through-hole H, achannel pattern 120 formed along an inner wall of the gate dielectriclayer GDb, and a gap-fill pattern 122 filling the interior of thechannel pattern 120. The channel pattern 120 may be in contact with asurface of the substrate 102, which is a bottom surface of thethrough-hole H, and an entire outer surface of the contact pad 124.

The gate dielectric layer GDb may include a tunneling layer 118enclosing the channel pattern 120, a charge trap layer 116 enclosing thetunneling layer 118, a barrier layer 114 enclosing the charge trap layer116, a protective layer 112 b surrounding the barrier layer 114,protective patterns 112 c that are integrally formed with the protectivelayer 112 b, extend toward the gate electrodes 134SS, 134C, and 134GS,and enclose one sides of the gate electrodes 134SS, 134C, and 134GS, andblocking layers 132 that are in contact with the protective patterns 112c and enclose the gate electrodes 134GS, 134C, and 134SS.

One surface of each blocking layer 132 may be in contact with an uppersurface GB1, a lower surface GB2, a first lateral surface GB4, a secondlateral surface GB5, and an upper inclined surface GB6 of each of thegate electrodes 134SS, 134C, and 134GS, and the other surface of eachblocking layer 132 may be in contact with parts of upper and lowersurfaces of each interlayer insulating layer 104 and an upper part BB1,a lower part BB2, and a body part BB3 of each protective pattern 112 c.

The protective layer 112 b and the protective patterns 112 c may includeoxidized silicon. The barrier layer 114 may include deposited siliconoxide. The oxidized silicon included in the protective layer 112 b andthe protective patterns 112 c may be more compact than the depositedsilicon oxide included in the barrier layer 114.

Since the protective layer 112 b is present, the upper part BB1, thelower part BB2, an inclined upper inner surface BB1 a, and an inclinedlower inner surface BB2 a of each protective pattern 112 c that is incontact with the lower and upper surfaces of the interlayer insulatinglayer 104, may be formed at a short length. This configuration may meanthat an area of the protective patterns 112 c enclosing the gateelectrodes 134SS, 134C, and 134GS within a desired (and/or alternativelypredetermined) space can be reduced, compared to that of thesemiconductor device 100A according to example embodiments.

Thus, as an area which the protective patterns 112 c occupy within thedesired (and/or alternatively predetermined) space is reduced, an areaof the gate electrode 134SS, 134C, and 134GS can be increased as such.Nevertheless, since one side of each of the gate electrodes 134SS, 134C,and 134GS can be formed in a shape in which a vertical width thereof isreduced, voids and seams in the gate electrodes 134SS, 134C, and 134GScan be reduced (and/or minimized).

FIG. 3A illustrates a cross-sectional view showing a vertical cell-typesemiconductor device according to example embodiments of inventiveconcepts. FIG. 3B illustrates an enlarged view of part D of FIG. 3A.

Referring to FIGS. 3A, 3B, and 1C, a vertical cell-type semiconductordevice 100C according to example embodiments of inventive concepts mayinclude a stacked structure 100S in which interlayer insulating layers104 and gate electrodes 134GS, 134C, and 134SS are alternately andrepeatedly stacked on a substrate 102, first to third capping layers110, 126, and 128 covering the stacked structure 100S, a through-hole Hpassing through the stacked structure 100S and the first capping layer110, a trench T passing through the stacked structure 100S and the firstto third capping layers 110, 126, and 128, first and second verticalstructures VS1 c and VS2 filling the through-hole H and the trench Trespectively, a contact pad 124 being in contact with the first verticalstructure VS1 c, a contact electrode 140 passing through the second andthird capping layers 126 and 128 to be in contact with the contact pad124, and a conductive interconnection 142 formed on an upper surface ofthe third capping layer 128 in contact with the contact electrode 140.

The first vertical structure VS1 c may include a gate dielectric layerGDc formed along an inner wall of the through-hole H, a cylindricalchannel pattern 120 formed along an inner wall of the gate dielectriclayer GDc, and a gap-fill pattern 122 filling the interior of thechannel pattern.

The gate dielectric layer GDc may include a tunneling layer 118enclosing the channel pattern 120, a charge trap layer 116 enclosing thetunneling layer 118, a protective layer 112 d enclosing the charge traplayer 116, protective patterns 112 e that are integrally formed with theprotective layer 112 d, extend toward the gate electrodes 134SS, 134C,and 134GS, and enclose one sides of the gate electrodes 134SS, 134C, and134GS, and blocking layers 132 that are located between the protectivepatterns 112 e and the gate electrodes 134GS, 134C, and 134SS andenclose the gate electrodes 134SS, 134C, and 134GS. Each blocking layer132 may enclose an upper surface, a lower surface, and one side of eachof the gate electrodes 134SS, 134C, and 134GS.

The protective layer 112 d and the protective patterns 112 e may includeoxidized silicon more compact than oxide included in the barrier layer114.

Since the protective layer 112 d is present, the time required for anoxidation process of forming the protective patterns 112 e can bereduced compared to the semiconductor device 100A according to exampleembodiments. As such, an upper part BB1, a lower part BB2, an upperinner surface BB1 a and a lower inner surface BB2 a of each protectivepattern 112 e that is in contact with lower and upper surfaces of theinterlayer insulating layer 104, may be formed at a short length. Thus,as described above, an area which the protective patterns 112 e occupyis reduced, an area of the gate electrode 134SS, 134C, and 134GS can beincreased as such. Nevertheless, since one side of each of the gateelectrodes 134SS, 134C, and 134GS may be formed in a shape in which avertical width thereof is reduced, voids and seams in the gateelectrodes 134SS, 134C, and 134GS can be reduced (and/or minimized).

Further, since the protective patterns 112 e and the protective layer112 d are formed between the gate electrodes 134GS, 134C, and 134SS andthe charge trap layer 116, they can replace a function of the barrierlayer 114 described above, and thus the barrier layer 114 can beomitted. In this case, a horizontal width W2 of the protective patterns112 e and the protective layer 112 d may be formed so as to be somewhatwider.

FIGS. 4A to 4Q illustrate process cross-sectional views showing a methodof fabricating the vertical cell-type semiconductor device according toexample embodiments of inventive concepts in a process sequence.

Referring to FIG. 4A, a method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include alternately stacking a plurality of interlayerinsulating layers 104 and a plurality of sacrificial layers 106 on asubstrate 102 to form a preliminary stacked structure 108, and stackinga first capping layer 110 on the preliminary stacked structure 108. Thesubstrate 102 may be formed of a semiconductor material, and include,for instance, a silicon (Si) substrate, a silicon germanium (SiGe)substrate, or a silicon-on-insulator (SOI) substrate. The interlayerinsulating layers 104 may include silicon oxide (SiO₂), and thesacrificial layers 106 may include silicon nitride (SiNx). Further, thefirst capping layer 110 may include silicon oxide (SiO₂).

Referring to FIG. 4B, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a through-hole H vertically passing throughthe preliminary stacked structure 108 and the first capping layer 110.An inner wall of the through-hole H may be exposed lateral surfaces ofthe interlayer insulating layers 104 and the sacrificial layers 106. Asurface of the substrate 102 may be a bottom surface of the through-holeH.

Referring to FIG. 4C, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include oxidizing the exposed sacrificial layers 106 toform protective patterns 112 a. The oxidation reaction of thesacrificial layers 106 may proceed from the lateral surfaces exposed tothe through-hole H. During the oxidation reaction, oxygen radicals maypenetrate into surfaces of the sacrificial layers 106, and interfaces ofthe sacrificial layers 106 and the interlayer insulating layers 104. Theoxygen radicals may penetrate along the interfaces of the sacrificiallayers 106 and the interlayer insulating layers 104 deeper than thesurfaces of the sacrificial layers 106. Thus, the protective patterns112 a may be shaped of an open square bracket ([) or a close squarebracket (]). A thickness of each protective pattern 112 a gets thinnerand thinner in proportion to a distance from the through-hole H. Incontrast, each sacrificial layer 106 may have a shape in which avertical width W3 thereof is reduced in inverse proportion to thedistance from the through-hole H. Each protective pattern 112 a may beformed so as to enclose parts of upper and lower surfaces of eachsacrificial layer 106, and a lateral surface of each sacrificial layer106. Further, each protective pattern 112 a may be in contact with partsof upper and lower surfaces of each interlayer insulating layer 104. Onevertical surface BB4 of each protective pattern 112 a may protrudetoward the center of the through-hole H. Here, during the oxidationreaction, the exposed surface of the substrate 102, which is the bottomsurface of the through-hole H, may also be subjected to the oxidationreaction.

The process of oxidizing the sacrificial layers 106 supplies the oxygenradicals to the exposed surfaces of the sacrificial layers 106. Theoxidation process may include a radical oxidation process. The radicaloxidation process may include an in-situ steam generation (ISSG)oxidation process and a plasma oxidation process. The ISSG oxidationprocess is a radical oxidation process using heat, and may use hydrogen(H₂) gas, oxygen (O₂) gas, or water vapor (H₂O) under low pressure at ahigh temperature of 800 to 1000° C. For example, oxygen radicals arepenetrated into the sacrificial layers 106 and then coupled with silicondangling bonds in the sacrificial layers 106, or an oxygen radical ispenetrated with a strong force, cuts a nitrogen atom coupled to asilicon atom and then is coupled to the silicon atom, and therebyoxidized silicon may be formed. The plasma oxidation process is aradical oxidation process using plasma, and may use a mixture gas ofargon (Ar), hydrogen, and oxygen gases, a mixture gas of argon andoxygen gases, a mixture gas of helium (He), hydrogen, and oxygen gases,a mixture gas of helium and oxygen gases, or a mixture gas of hydrogenand oxygen gases. The plasma oxidation process may proceed at a lowertemperature compared to the ISSG oxidation process. In the plasmaoxidation process, temperature and pressure conditions may be adjustedin order to enhance the penetration of the oxygen radicals. The oxideformed in the oxidation process has a more compact composition and astronger bond than that formed in a deposition process, and thus isexcellent in chemical and physical durability. For example, the oxideformed in the oxidation process may have more excellent etchingresistance than that formed in the deposition process.

Referring to FIG. 4D, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include conformally forming a first dielectric layer 114 aon the exposed lateral surfaces of the protective patterns 112 a,interlayer insulating layers 104, and the first capping layer 110 in thethrough-hole H and on an upper surface of the first capping layer 110,conformally forming a second dielectric layer 116 a on an upper surfaceof the first dielectric layer 114 a, and conformally forming a thirddielectric layer 118 a on an upper surface of the second dielectriclayer 116 a. The first dielectric layer 114 a may include silicon oxide,and the second dielectric layer 116 a may include silicon nitride(SiNx). Further, the third dielectric layer 118 a may include siliconoxide or nitrogen-doped silicon oxide.

Referring to FIG. 4E, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a barrier layer 114, a charge trap layer116, and a tunneling layer 118 in the through-hole H. The process offorming the barrier layer 114, the charge trap layer 116, and thetunneling layer 118 may include performing an etch-back process on thefirst to third dielectric layers 114 a, 116 a, and 118 a to remove thethird, second, and first dielectric layers 118 a, 116 a, and 114 a onthe first capping layer 110. The first to third dielectric layers 114 a,116 a, and 118 a formed on the first capping layer 110 may be removed byan overall anisotropic etching process(the etch back process), andthereby the barrier layer 114 that are in contact with the verticallateral surfaces of the interlayer insulating layers 104, the chargetrap layer 116 and the tunneling layer 118, may be formed. Further,during the etching process, the upper surface of the substrate 102 maybe exposed at the bottom of the through-hole H.

Referring to FIG. 4F, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a channel layer 120 a along the uppersurface of the substrate 102 which is exposed at the bottom of thethrough-hole H, a surface of the tunneling layer 118, and lateral andupper surfaces of the first capping layer 110, and forming a gap-filllayer 122 a on a surface of the channel layer 120 a so as to fill theinterior of the through-hole H. The process of forming the channel layer120 a may include a chemical vapor deposition (CVD) process, such as anatomic layer deposition (ALD) process. The channel layer 120 a may beformed in a polycrystalline state by continuous heat treatment. Thus,the channel layer 120 a may include polysilicon. The gap-fill layer 122a may include an insulating material, such as silicon oxide.

Referring to FIG. 4G, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a gap-fill pattern 122 filling part of thethrough-hole H, and forming a contact layer 124 a on upper surfaces ofthe gap-fill pattern 122 and the channel layer 120 a. The process offorming the gap-fill pattern 122 may include removing a part of thegap-fill layer 122 a using an etch-back process so as to remain only inthe through-hole H. A surface of the gap-fill pattern 122 may be locatedlower than that of the first capping layer 110. The contact layer 124 amay include polysilicon.

Referring to FIG. 4H, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a contact pad 124 and a channel pattern 120in the through-hole H. The process of forming the contact pad 124 andthe channel pattern 120 may include a planarization process of partlyremoving the contact layer 124 a and the channel layer 120 a to exposethe upper surface of the first capping layer 110, for instance achemical mechanical polishing (CMP) process.

Referring to FIG. 4I, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a second capping layer 126 and a thirdcapping layer 128 on the through-hole H and the first capping layer 110.The second and third capping layers 126 and 128 may have an etchselectivity with respect to the sacrificial layers 106. For example, ifthe sacrificial layers 106 are formed of silicon nitride, the second andthird capping layers 126 and 128 may include silicon oxide.

Referring to FIG. 4J, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a trench T, which passes through the firstto third capping layers 110, 126, and 128, and the preliminary stackedstructure 108, at a position spaced apart from the through-hole H.

Referring to FIG. 4K, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include removing the sacrificial layers 106 located betweenthe interlayer insulating layers 104 in the trench T to form interlayerspaces 130. As an etchant for removing the sacrificial layers 106,phosphoric acid (H₃PO₄) may be used. After the sacrificial layers 106are removed using the phosphoric acid, a cleaning process using standardclean 1 (SC-1) may further proceed. Here, in the process of removing thesacrificial layers 106 using the phosphoric acid (H₃PO₄), the protectivepatterns 112 a may be exposed. The protective patterns 112 a can limit(and/or prevent) the phosphoric acid (H₃PO₄) from penetrating theinterior of the through-hole H to cause damage to the barrier layer 114and the charge trap layer 116.

Referring to FIG. 4L, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include conformally forming a fourth dielectric layer 132 aon the exposed surfaces of the interlayer insulating layers 104 and thefirst to third capping layers 110, 126, and 128 which are exposed to thetrench T. The fourth dielectric layer 132 a may include aluminum oxide(Al₂O₃) or hafnium oxide (HfO).

Referring to FIG. 4M, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a conductive layer 134 a on the fourthdielectric layer 132 a. The conductive layer 134 a may be formed so asto fill the interlayer spaces 130 (see FIG. 4L). A material of which theconductive layer 134 a is formed may include a doped semiconductor suchas doped silicon, a metal such as tungsten (W), copper (Cu), or aluminum(Al), conductive metal nitride such as titanium nitride (TiN) ortantalum nitride (TaN), a conductive metal-semiconductor compound suchas metal silicide, or transition metal such as titanium (Ti) or tantalum(Ta). For example, the conductive layer 134 a may include tungsten (W)or titanium nitride (TiN).

Referring to FIG. 4N, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include partly removing the conductive layer 134 a to forma plurality of gate electrodes 134SS, 134C, and 134GS. The gateelectrodes 134SS, 134C, and 134GS may include a ground selection gateelectrode 134GS located at a lowermost side so as to be adjacent to thesubstrate 102, a string selection gate electrode 134SS located at anuppermost side, and cell gate electrodes 134C located between the groundselection gate electrode 134GS and the string selection gate electrode134SS. Here, the number of cell gate electrodes 134C may be 2^(n) (n isthe natural number). The gate electrodes 134SS, 134C, and 134GS may eachbe formed in a shape in which a vertical width thereof is reduced withthe approach to the through-hole H.

Referring to FIGS. 4O and 1C, the method of fabricating the verticalcell-type semiconductor device 100A according to example embodiments ofinventive concepts may include partly removing the fourth dielectriclayer 132 a to form blocking layers 132 enclosing the gate electrodes134GS, 134C, and 134SS. One surface of each blocking layer 132 may be incontact with an upper surface GB1, a lower surface GB2, an upperinclined surface GB5, a lower inclined surface GB6, and a second lateralsurface GB4 of each of the gate electrodes 134GS, 134C, and 134SS, andthe other surface of each blocking layer 132 may be in contact withparts of the upper and lower surfaces of the interlayer insulating layer104 and the protective patterns 112 a.

Referring to FIG. 4P, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a second vertical structure VS2 in thetrench T, and forming a via 138 exposing the contact pad 124. The secondvertical structure VS2 may include silicon oxide (SiO₂).

Referring to FIG. 4Q, the method of fabricating the vertical cell-typesemiconductor device 100A according to example embodiments of inventiveconcepts may include forming a contact electrode 140 that fills the via138 and is in contact with the contact pad 124, and forming a conductiveinterconnection 142 extending along an upper surface of the thirdcapping layer 128 in contact with the contact electrode 140. The contactelectrode 140 and the conductive interconnection 142 may include aconductive material, such as copper (Cu), tungsten (W), or aluminum(Al).

FIGS. 5A to 5F illustrate process cross-sectional views showing a methodof fabricating the vertical cell-type semiconductor device according toexample embodiments of inventive concepts in a process sequence.

Referring to FIG. 5A, a method of fabricating the vertical cell-typesemiconductor device 100B according to example embodiments of inventiveconcepts may include alternately stacking a plurality of interlayerinsulating layers 104 and a plurality of sacrificial layers 106 on asubstrate 102 to form a preliminary stacked structure 108, and forming afirst capping layer 110 on the preliminary stacked structure 108 Theinterlayer insulating layers 104 may include silicon oxide, and thesacrificial layers 106 may include silicon nitride.

Referring to FIG. 5B, the method of fabricating the vertical cell-typesemiconductor device 100B according to example embodiments of inventiveconcepts may include forming a through-hole H vertically passing throughthe first capping layer 110 and the preliminary stacked structure 108.An inner wall of the through-hole H may correspond to exposed lateralsurfaces of the interlayer insulating layers 104 and the sacrificiallayers 106. The surface of the substrate 102 may be a bottom surface ofthe through-hole H.

Referring to FIG. 5C, the method of fabricating the vertical cell-typesemiconductor device 100B according to example embodiments of inventiveconcepts may include forming a first dielectric layer 112 baa on theinner wall of the through-hole H. The first dielectric layer 112 baa mayinclude silicon nitride (SiN_(X)).

Referring to FIG. 5D, the method of fabricating the vertical cell-typesemiconductor device 100B according to example embodiments of inventiveconcepts may include oxidizing the first dielectric layer 112 baa and apart of each sacrificial layer 106 to form an oxide layer 112 ba, andforming protective patterns 112 c, each of which extends from the oxidelayer and encloses a part of each sacrificial layer 106. Here, theprocess of oxidizing the first dielectric layer 112 baa and thesacrificial layers 106 may include causing oxygen radicals to penetratethe first dielectric layer 112 baa and the sacrificial layers 106 toreact with silicon atoms. The oxidation reaction begins from a surfaceof the first dielectric layer 112 baa to proceed to a part of eachsacrificial layer 106.

In comparison with the semiconductor device 100A as described above,each protective pattern 112 c formed by oxidizing a part of eachsacrificial layer 106, may be formed at a short length E at which it isin contact with lower and upper surfaces of each interlayer insulatinglayer 106. This is because the oxide layer 112 ba blocks or screens theoxygen radicals penetrating into an interface between the interlayerinsulating layer 104 and each sacrificial layer 106. Thus, depending onthe thickness of the first dielectric layer 112 baa, a thickness of theoxide layer 112 ba and a profile of each protective pattern 112 c may beadjusted.

Referring to FIG. 5E, the method of fabricating the vertical cell-typesemiconductor device 100B according to example embodiments of inventiveconcepts may include conformally forming a second dielectric layer 114 aon the exposed surface of the oxide layer 112 ba, conformally forming athird dielectric layer 116 a on the second dielectric layer 114 a, andconformally forming a fourth dielectric layer 118 a on the thirddielectric layer 116 a. The second dielectric layer 114 a may includesilicon oxide, and the third dielectric layer 116 a may include siliconnitride. Further, the fourth dielectric layer 118 a may include siliconoxide or nitrogen-doped silicon nitride.

Referring to FIG. 5F, the method of fabricating the vertical cell-typesemiconductor device 100B according to example embodiments of inventiveconcepts may include forming a protective layer 112 b, a barrier layer114, a charge trap layer 116, and a tunneling layer 118 in thethrough-hole H. The process of forming the protective layer 112 b, thebarrier layer 114, the charge trap layer 116, and the tunneling layer118 may include an overall anisotropic etching process of partlyremoving the oxide layer 112 ba and the second to fourth dielectriclayers 114 a, 116 a, and 118 a so that the oxide layer 112 ba and thesecond to fourth dielectric layers 114 a, 116 a, and 118 a are left onlyon the inner wall of the through-hole H. Due to the overall anisotropicetching process, the oxide layer 112 ba may be etched to form theprotective layer 112 b that is in contact with the inner wall of thethrough-hole H, and the second dielectric layer 114 a may be etched toform the barrier layer 114 that is in contact with the protective layer112 b. Further, the third dielectric layer 116 a may be etched to formthe charge trap layer 116 that is in contact with the barrier layer 114,and the fourth dielectric layer 118 a may be etched to form thetunneling layer 118 that is in contact with the charge trap layer 116.The following processes are equal to those described with reference toFIGS. 4F to 4Q, and description thereof will be omitted.

FIGS. 6A to 6D illustrate process cross-sectional views showing a methodof fabricating a vertical cell-type semiconductor device according toexample embodiments of inventive concepts in a process sequence.

Referring to FIG. 6A, a method of fabricating a vertical cell-typesemiconductor device 100C according to example embodiments of inventiveconcepts may include alternately stacking a plurality of interlayerinsulating layers 104 and a plurality of sacrificial layers 106 on asubstrate 102 to form a preliminary stacked structure 108, forming afirst capping layer 110 on the preliminary stacked structure 108, andforming a through-hole H passing through the first capping layer 110 andthe preliminary stacked structure 108. Further, the method may includeforming a first dielectric layer 112 daa on an inner wall of thethrough-hole H. The first dielectric layer 112 daa may include siliconnitride.

Referring to FIG. 6B, the method of fabricating the vertical cell-typesemiconductor device 100C according to example embodiments of inventiveconcepts may include oxidizing the first dielectric layer 112 daa and apart of each sacrificial layer 106 to form an oxide layer 112 da, andforming protective patterns 112 e extending from the oxide layer 112 da.Here, the process of oxidizing the first dielectric layer 112 daa andthe interlayer insulating layer 104 may include causing oxygen radicalsto penetrate the first dielectric layer and the interlayer insulatinglayer 104 to react with silicon atoms. The oxidation reaction of thesilicon atoms may begin from a surface of the first dielectric layer 112daa to proceed to a part of each sacrificial layer 106. The protectivepatterns 112 e may be formed by the oxidation reaction.

Referring to FIG. 6C, a method of fabricating the vertical cell-typesemiconductor device 100C according to example embodiments of inventiveconcepts may include conformally forming a second dielectric layer 116 aon the exposed surface of the oxide layer 112 da, and conformallyforming a third dielectric layer 118 a on the second dielectric layer116 a. The second dielectric layer 116 a may include silicon nitride,and the third dielectric layer 118 a may include silicon oxide.

Referring to FIG. 6D, the method may include etching an oxide layer 112da, a trap dielectric layer 114 a, and a tunneling dielectric layer 116a to form a protective layer 112 d, a charge trap layer 116, and atunneling layer 118. The protective layer 112 d and the protectivepatterns 112 e has etching resistance to an etchant for removing thesacrificial layers 106, and simultaneously performs a barrier function.For example, the barrier layer 114 may be omitted. The followingprocesses are equal to those described with reference to FIGS. 4F to 4Q,and description thereof will be omitted.

FIG. 7 illustrates a conceptual view showing a semiconductor module,which includes a semiconductor devices according to example embodimentsof inventive concepts.

Referring to FIG. 7, a semiconductor module 500 according to exampleembodiments of inventive concepts may include a semiconductor deviceaccording to example embodiments of inventive concepts (e.g., one of thesemiconductor devices 100A, 100B, and 100C according to exampleembodiments of inventive concept) that is mounted on a semiconductormodule board 510. The semiconductor module 500 may further include amicroprocessor 520 mounted on the module board 510. Input/outputterminals 540 may be disposed on at least one side of the module board510. The semiconductor module 500 may include a memory card or a solidstate drive (SSD).

FIG. 8 illustrates a conceptual block diagram showing an electromagneticsystem, which includes a semiconductor devices according to exampleembodiments of inventive concepts.

Referring to FIG. 8, one of the semiconductor devices 100A, 100B, and100C according to example embodiments of inventive concepts may beapplied to an electromagnetic system 600. The electromagnetic system 600may include a body 610, a microprocessor unit 620, a power distributor630, a function unit 640, and/or a display controller unit 650. The body610 may be a system board or a motherboard having a printed circuitboard (PCB). The microprocessor unit 620, the power distributor 630, thefunction unit 640, and the display controller unit 650 may be mounted onthe body 610. A display unit 660 may be disposed on the top of the body610 or outside the body 610. For example, the display unit 660 may bedisposed on a surface of the body 610, and display an image processed bythe display controller unit 650. The power supply 630 may be suppliedwith a desired (and/or alternatively predetermined) voltage from anexternal power supply, divide the voltage into various levels, andsupply those voltages to the microprocessor unit 620, the function unit640, and the display controller unit 650. The function unit 640 mayperform various functions of the electromagnetic system 600. Forexample, if the electromagnetic system 600 is a mobile electromagneticappliance such a mobile phone, the function unit 640 may include variouscomponents that can perform wireless communication functions such asimage output, or voice output to a speaker, by dialing or communicationwith an external apparatus 670. If the electromagnetic system 600includes a camera, the function unit 640 may serve as an imageprocessor. In example embodiments, if the electromagnetic system 600 isconnected to a memory card for capacity expansion, the function unit 640may be a memory card controller. The function unit 640 may send/receivea signal to/from the external apparatus 670 via a wired or wirelesscommunication unit 680. Further, if the electromagnetic system 600requires a universal serial bus (USB) for function expansion, thefunction unit 640 may serve as an interface controller. One of thesemiconductor devices 100A, 100B, and 100C according to exampleembodiments of inventive concepts may be included in the function unit640.

FIG. 9 illustrates a schematic block diagram showing an electromagneticsystem, including a semiconductor device according to exampleembodiments of inventive concepts.

Referring to FIG. 9, an electromagnetic system 700 may include one ofthe semiconductor devices 100A, 100B, and 100C described previously.

The electromagnetic system 700 may be applied to a mobileelectromagnetic appliance or a computer. For example, theelectromagnetic system 700 may include a memory 712, a microprocessor714, and a user interface 718 performing data communication using arandom access memory (RAM) 716 and a bus 720. The microprocessor 714 mayprogram and control the electromagnetic system 700. The RAM 716 may beused as an operation memory of the microprocessor 714. For example, themicroprocessor 714 or the RAM 716 may include one of the semiconductordevices 100A, 100B, and 100C according to example embodiments ofinventive concepts.

The microprocessor 714, the RAM 716, and/or other components may beassembled in a single package. The user interface 718 may be used toinput/output data to/from the electromagnetic system 700. The memory 712may store codes for operating the microprocessor 714, data processed bythe microprocessor 714, or external input data. The memory 712 mayinclude a controller and a memory.

FIG. 10 schematically shows a mobile electromagnetic appliance, whichincludes one of the semiconductor devices according to exampleembodiments of inventive concepts. The mobile electromagnetic appliance800 may be understood to be a tablet personal computer (PC). Inaddition, at least one of the semiconductor devices 100A, 100B, and 100Caccording to example embodiments of inventive concepts may be used for aportable computer, such as a laptop computer, a MPEG-1 or MPEG-2 AudioLayer III (MP3) player, an MP4 player, a navigation device, a solidstate disk (SSD), a desktop computer, a vehicle, and a householdelectric appliance, in addition to the tablet PC.

According to example embodiments of inventive concepts, the protectivepatterns can reduce (and/or prevent) a wet etching solution from causingdamage to the gate dielectric layers (charge trap layer, tunnelinglayer, etc.) and the channel pattern.

Further, since each protective pattern is formed within a desired(and/or alternatively predetermined) space so as to enclose one side ofeach gate electrode, each gate electrode can be formed in a shape inwhich the vertical width thereof is reduced with the approach to oneside thereof. In this case, no or minimum voids or seams can be presentin each gate electrode.

The foregoing disclosure is illustrative of example embodiments ofinventive concepts and is not to be construed as limiting thereof.Although a few embodiments have been described, those skilled in the artwill readily appreciate that many modifications are possible withoutmaterially departing from the scope of the claims. Accordingly, all suchmodifications are intended to be included within the scope of exampleembodiments of inventive concepts as defined in the claims. In theclaims, means-plus-function clauses are intended to cover the structuresdescribed herein as performing the recited function, and not onlystructural equivalents but also equivalent structures.

1.-20. (canceled)
 21. A semiconductor device, comprising: a substrate; astacked structure including interlayer insulating layers and gateelectrodes alternately stacked on the substrate, the stacked structuredefining a through-hole, each of the gate electrodes including a portionin which a vertical width thereof is reduced with the approach to oneend thereof; blocking layers between the interlayer insulating layersand the gate electrodes; and a vertical structure in the through-hole,the vertical structure including a gap-fill pattern in a middle of thethrough-hole, a channel pattern surrounding an outer surface of thegap-fill pattern, and a gate dielectric layer surrounding an outersurface of the channel pattern, wherein the gate dielectric layerincludes a tunneling layer in contact with the channel pattern, a chargetrap layer in contact with the tunneling layer, a barrier layer incontact with the charge trap layer, and protective patterns beingbetween the barrier layer and one of the gate electrodes, each one ofthe protective patterns extending between two of the interlayerinsulating layers, and wherein the protective patterns include an oxideof silicon.
 22. The semiconductor device of claim 21, wherein theblocking layers includes a dielectric material having a metal.
 23. Thesemiconductor device of claim 22, wherein the blocking layers includealuminum oxide or hafnium oxide.
 24. The semiconductor device of claim21, wherein the protective patterns is a higher density than the barrierlayer.
 25. The semiconductor device of claim 21, wherein each of theportions of the gate electrodes includes an upper inclined surface and alower inclined surface opposite to the upper inclined surface, andwherein each one of the protective patterns extends between one of theinterlayer insulating layers and the upper inclined surface of theportion of one of the gate electrodes, and between one of the interlayerinsulating layers and the lower inclined surface of the portion of oneof the gate electrodes.
 26. The semiconductor device of claim 25,wherein each of the gate electrode further includes an upper surfaceopposite to a lower surface, and wherein the blocking layers extendsbetween one of the interlayer insulating layer and the upper surface ofone of the gate electrodes, and between one of the interlayer insulatinglayer and the lower surface of one of the gate electrode.
 27. Thesemiconductor device of claim 21, wherein each one of the protectivepatterns includes a protrusion protruding into the through-hole.
 28. Thesemiconductor device of claim 27, wherein the barrier layer contactsexposed lateral surfaces of the interlayer insulating layers, and theprotrusions of the protective patterns.
 29. The semiconductor device ofclaim 21, wherein a horizontal distance between the portion of one ofthe gate electrodes and the channel layer is greater than a horizontaldistance between the channel layer to one of the interlayer insulatinglayers.
 30. The semiconductor device of claim 21, further comprising: acontact electrode on the gap-fill pattern and contacting the channelpattern.
 31. The semiconductor device of claim 30, further comprising:capping layers on the stacked structure, wherein the capping layersdefine a hole exposing an upper surface of the contact electrode. 32.The semiconductor device of claim 31, further comprising: a conductiveinterconnection on the capping layers, wherein the conductiveinterconnection is electrically connected to the exposed upper surfaceof the contact electrode.
 33. A semiconductor device, comprising: asubstrate; a stacked structure including interlayer insulating layersand gate electrodes alternately stacked on the substrate, the stackedstructure defining a through-hole, each of the gate electrodes includinga portion in which a vertical width thereof is reduced with the approachto one end thereof; blocking layers between the interlayer insulatinglayers and the gate electrodes; a gap-fill pattern in a middle of thethrough-hole; a channel pattern surrounding an outer surface of thegap-fill pattern; and a gate dielectric layer between the stackedstructure and the channel pattern, the gate dielectric layer includes atunneling layer in contact with the channel pattern, a charge trap layerin contact with the tunneling layer, a protective layer in contact withthe charge trap layer, protective patterns that are integral with theprotective layer, the protective patterns extending to the gateelectrodes.
 34. The semiconductor device of claim 33, wherein each ofthe blocking layers extends between the gate electrodes and the gatedielectric layer.
 35. The semiconductor device of claim 33, wherein theprotective patterns include an oxide of silicon, the charge trap layerincludes one of silicon nitride, aluminum oxide, zirconium oxide,hafnium oxide, lanthanum oxide, and the tunneling layer includes one ofsilicon oxide and nitrogen-doped silicon oxide.
 36. A semiconductordevice, comprising: a substrate; interlayer insulating layers on thesubstrate; gate electrodes between the interlayer insulating layers,each of the gate electrode including a first portion having a firstlateral surface, and a second portion having a second lateral surfaceopposite to the first lateral surface, a length of the first lateralsurface being shorter than a length of the second lateral surface;blocking layers between the interlayer insulating layers and the secondportions of the gate electrodes; a channel pattern on the first portionsof the gate electrodes, the channel pattern extending on lateralsurfaces of the interlayer insulating layers; and a gate dielectriclayer extending vertically over the substrate between interlayerinsulating layers and the channel pattern, the gate dielectric layerincluding protective patterns between the channel pattern and theblocking layers, the protective patterns extending between theinterlayer insulating layers and the first portions of the gateelectrodes.
 37. The semiconductor device of claim 36, wherein the firstportions of the gate electrodes each have a thickness that graduallyreduces from the second portions of the gate electrodes towards the gatedielectric layer.
 38. The semiconductor device of claim 36, wherein theprotective patterns include an oxide of silicon, the interlayerinsulating layers include an oxide, and the oxide of silicon in theprotective patterns is more compact than the oxide of the interlayerinsulating layers.
 39. The semiconductor device of claim 36, furthercomprising: a protective layer that extends vertically over thesubstrate, the protective layer extending between the gate dielectriclayer and the protective patterns, and between the interlayer insulatinglayer and the gate dielectric layer.
 40. The semiconductor device ofclaim 39, wherein a material of the protective layer is the same as amaterial of the protective patterns.